Vimal William

I'm a system software engineer at SandLogic Tech in Bangalore, where I work on the software stack for Deep Learning accelerators which includes SandLogic's AI optimiser and AI compilers

At SandLogic, I worked on the low-latency FPGA-based streaming framework and heterogeneous hardware-accelerator Computer-Vision(CV) pipelines. I completed Bachelor's in Electronics Engineering from Anna University.

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Research

I'm interested in neural network compression & optimization, SW/HW co-design for AI accelerators, hardware-aware AI optimization, graph compilers. On-going research & projects are highlighted.

*Currently a part of low-power hardware systems group for research on SW/HW co-desig for activation engine and works on mapping NeRF model on FPGAs

Focused on the minimal implementation for a graph compiler based on MLIR stack and the follows the approaches proposed by the TVM white-paper and currently focusing on the backend targetting NVPTX.

GStreamer-based streaming pipeline dedicated for on-device object detection supports CPU/GPU INT8 inference

Applying DFT and ICA to condition the nosiy signals from the motor-cortex region and utilize SOTA AI models to predict the associated motor actions.

Study on the effects of different windows on the MFCC Algorithm for speech signal processing.

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